1. Technical Field
The present invention relates to a comparator circuit used in a semiconductor integrated circuit.
2. Related Art
There are many cases in which a circuit that detects voltage level is necessary in a semiconductor integrated circuit, and a comparator circuit is used when configuring the voltage detector circuit. Also, in recent years, there has been a strong demand for a reduction in current consumption in circuits, and a further reduction in current consumption is being sought in comparator circuits too.
FIG. 8 is a diagram showing a configuration of a heretofore known comparator circuit. Hereafter, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be abbreviated as PMOSFET, and an n-channel MOSFET as NMOSFET.
In the heretofore known comparator circuit shown in FIG. 8, a PMOSFET 133, a PMOSFET 134, and a PMOSFET 142 form a first current mirror circuit, and an NMOSFET 131, an NMOSFET 132, and an NMOSFET 139 form a second current mirror circuit. A resistor 122, the PMOSFET 133 and PMOSFET 134 of the first current mirror circuit, and the NMOSFET 131 and NMOSFET 132 of the second current mirror circuit form a bias circuit 120 that supplies a bias current to a differential circuit 110 shown hereafter. Also, a PMOSFET 135, a PMOSFET 136, an NMOSFET 137, and an NMOSFET 138 form the differential circuit 110. Herein, the NMOSFET 137 and NMOSFET 138 form a third current mirror circuit. Furthermore, an NMOSFET 141 and a PMOSFET 142 form an output circuit 140. Also, the NMOSFET 139 and a Zener diode 124 form a reference voltage generator circuit 130.
In FIG. 8, the resistor 122, the NMOSFET 131, the NMOSFET 132, and the PMOSFET 133 are used in order to cause a bias current to flow through the PMOSFET 134 of FIG. 8. That is, the current flowing through the drain of the PMOSFET 134 is of the same magnitude as the current flowing through the drain of the PMOSFET 133 forming the first current mirror circuit, and it is the resistor 122, and the NMOSFET 131 and NMOSFET 132 forming the second current mirror circuit, that determine the value of the current flowing through the drain of the PMOSFET 133.
That is, the current flowing through the drain of the NMOSFET 131 forming the second current mirror circuit is of the same magnitude as the current flowing through the drain of the NMOSFET 132, and the value of the current flowing through the drain of the NMOSFET 132 is controlled via the resistor 122. The source of each of the NMOSFET 131 and NMOSFET 132 is connected to a power source terminal Ve (herein, it is taken that the power source terminal Ve is set at a ground GND).
As the drain and gate of the NMOSFET 132 are diode-connected in the example shown, a voltage applied to the resistor 122 is (a power source voltage Vb of a power source Vb—a gate to source voltage Vgs of the NMOSFET 132), and this determines the current flowing through the resistor 122. Then, the current flowing through the resistor 122 determines the bias current flowing to the differential circuit 110 via the first and second current mirrors. With the diode-connected NMOSFET 132, as the square of the gate to source voltage Vgs and the current flowing through the NMOSFET 132 are proportional, the source voltage Vgs does not change greatly even in the event that the current flowing through the NMOSFET 132 changes, meaning that, when the power source voltage Vb changes, most of the amount of change is applied to the resistor 122. Consequently, the configuration is such that the supply of the bias current by the bias circuit 120 is inevitably affected in no small degree by the voltage fluctuation of the power source Vb.
Also, as the second current mirror circuit is configured to include the NMOSFET 139, a drain current proportional to the drain current of the NMOSFET 132 flows through the NMOSFET 139. Also, a voltage applied to a common connection point linking the constant voltage device (the Zener diode 124) forming the reference voltage generator circuit 130 and the drain of the NMOSFET 139 is a voltage wherein a certain voltage (the Zener voltage of the Zener diode 124) is subtracted from the voltage of the power source Vb (hereafter, this will be called a reference voltage (REF)), and this is maintained constant unless there is a fluctuation in the power source voltage Vb.
In FIG. 8, the drain of the PMOSFET 134 is connected to the sources of the PMOSFET 135 and PMOSFET 136 forming a differential pair. The reference voltage REF is input into the gate of the PMOSFET 136, and an input signal Vin used for comparison is input via an input terminal IN into the gate of the PMOSFET 135. Also, the drain of the PMOSFET 135 is connected to the drain and gate of the NMOSFET 138, and also to the gate of the NMOSFET 137, and the drain of the PMOSFET 136 is connected to the drain of the NMOSFET 137. The sources of the NMOSFET 137 and NMOSFET 138 are connected to the power source terminal Ve (the ground GND). Also, the drains of the PMOSFET 136 and NMOSFET 137 are connected to the gate of the NMOSFET 141 forming the output circuit 140, and the drain of the NMOSFET 141 is connected to the drain of the PMOSFET 142. The source of the NMOSFET 141 is connected to the power source terminal Ve (the ground GND). Also, the drain of the NMOSFET 141 and the drain of the PMOSFET 142 are connected to an output terminal OUT.
As heretofore described, the PMOSFET 135, PMOSFET 136, NMOSFET 137, and NMOSFET 138 form the differential circuit 110 and, when the input signal Vin applied to the input terminal IN becomes higher than the reference voltage REF, the impedance of the PMOSFET 136 decreases relatively (e.g. correspondingly). Meanwhile, as the impedance of the PMOSFET 135 increases relatively (e.g., correspondingly), and the current flowing through the PMOSFET 135 decreases, the gate voltage of the NMOSFET 137 decreases, and the impedance of the NMOSFET 137 increases. Owing to the balance between the PMOSFET 136 whose impedance has decreased and the NMOSFET 137 whose impedance has increased, the gate voltage of the NMOSFET 141, which is the potential of the connection point of the NMOSFET 137 and PMOSFET 136, increases, the NMOSFET 141 is turned on, and the voltage of the output terminal OUT is of a low level (L level).
Meanwhile, as the impedance of the PMOSFET 136 increases while the impedance of the PMOSFET 135 decreases when the input signal Vin applied to the input terminal IN becomes lower than the reference voltage REF, the gate voltage of the NMOSFET 137 increases, the impedance of the NMOSFET 137 decreases, the gate voltage of the NMOSFET 141 decreases, the NMOSFET 141 is turned off, and the voltage of the output terminal OUT is of high level (H level).
FIG. 9 is a diagram showing a state of the current consumption of the heretofore known comparator circuit shown in FIG. 8. In FIG. 9, when the power source voltage (the voltage between Vb and Ve) is 15V, the bias current flowing into the differential circuit is 51 μA, and it can be seen that the current consumption is high in comparison with the case of the invention (when the power source voltage (the voltage between Vb and Ve) is 15V, the bias current flowing into the differential circuit is 28 μA, as shown in FIG. 5), to be described hereafter. Herein, the input signal Vin applied to the input terminal IN is obtained from a common connection point linking two resistors (not shown) that connect the power source voltages Vb and Ve in series.
In response to this, in order to achieve a balance between a low current consumption and a high-speed response, a comparator circuit shown in FIG. 1 of JP-A-2002-217691 normally reduces the current consumption by suppressing the bias current flowing through a p-channel MOSFET 3, and when it is detected that the values of the two inputs of the comparator circuit are near, the bias current is enhanced by a bias enhancing circuit A, achieving an increase in speed.
As shown by the graph of FIG. 9 showing the state of the current consumption, the heretofore known comparator circuit shown in FIG. 8 is such that, as the bias current (the consumed current) flowing into the differential circuit increases when the input signal Vin increases, it is difficult to say that it is a comparator circuit that enables a realization of reduced current consumption, and there is a demand for the realization of a comparator circuit with which a further reduction in current consumption is possible.
Also, in JP-A-2002-217691, the current consumption at a certain power source voltage is reduced by suppressing the current value of a current source 2 shown in FIG. 1 of JP-A-2002-217691. However, when the power source voltage is increased, it is difficult to suppress a rise in the current consumption. Although a configuration making the current value of the current source 2 shown in FIG. 1 of JP-A-2002-217691 a constant current that does not depend on the power source voltage is not impossible, the current consumption of a circuit for maintaining a constant current increases when increasing the power source voltage, and it is inevitable that the overall configuration is such that the current consumption increases when the power source voltage increases.
Furthermore, compared to the heretofore known comparator circuit, the comparator circuit of JP-A-2002-217691 is of a complex circuit configuration because it includes the bias enhancing circuit, and the like.